The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, stricter demands have been placed on lithography process. For example, techniques such as immersion lithography, multiple patterning, extreme ultraviolet (EUV) lithography, and e-beam lithography have been utilized to support critical dimension (CD) requirements of the smaller devices. In particular, one such example is high throughout electron beam writer systems operable to use mask-less lithography processes. This e-beam system may use complementary-meta-oxide-semiconductor (CMOS) devices with an array of controllable pixels, which can act as an array of electron mirrors. Using this device, the system can generate a pattern to be written on a target substrate by reflecting an electron beam off the array of mirrors where the pixels of the array are turned off or on. The size of the patterned image is dependent on the pixel size however, and typical pixel sizes are limited due to the functionality required by each pixel. Accordingly, although existing lithography methods have been generally adequate, they have not been satisfactory in all respects.